Lead Analog Layout Design Engineer (SerDes)
experience and design experience at 10Gbps and in 16nm technologies * Collaborating with the Cadence R&D teams (Virtuoso, PVS
experience and design experience at 10Gbps and in 16nm technologies * Collaborating with the Cadence R&D teams (Virtuoso, PVS
, Katowice, Edinburgh Reports to: Senior Principal Engineer The Role: We are seeking an exceptional Principal Digital... and senior engineers to understand functional and performance requir…
experience and design experience at 10Gbps and in 16nm technologies * Collaborating with the Cadence R&D teams (Virtuoso, PVS
Review Meetings and Checklist Reviews as part of ISO-9001. Represent Cadence in Standards Body Working Groups e.g. IEEE, PCI
front-end flows Collaborate with R&D, Product Engineering and Marketing teams to drive product improvements and increase
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