Principal Design Engineer
and inclusion in the workplace. Travel: 10% We’re doing work that matters. Help us solve what others can’t.
and inclusion in the workplace. Travel: 10% We’re doing work that matters. Help us solve what others can’t.
to challenging customer and internal silicon problems. Technical Scope Depending on experience, the role may encompass areas
, Katowice, Edinburgh Reports to: Senior Principal Engineer The Role: We are seeking an exceptional Principal Digital... and senior engineers to understand functional and performance requir…
to make an impact on the world of technology. Job Title: Principal Digital Implementation Engineer Location: Munich, Cork..., Katowice, Edinburgh Reports to: Senior Principal Engineer The R…
and inclusion in the workplace. Travel: 10% We’re doing work that matters. Help us solve what others can’t.
experience and design experience at 10Gbps and in 16nm technologies * Collaborating with the Cadence R&D teams (Virtuoso, PVS
: Design of High Speed SERDES for UCIe products at data rates up to 64 Gbps on leading edge technology nodes (e.g. 2nm FinFET
to make an impact on the world of technology. Job Title: Lead Analog Layout Design Engineer (SERDES/UCie) Location: Cork... Reports to: Sr Principal Engineer Job Overview: The Lead Analog L…
SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock
and inclusion in the workplace. Travel: 10% We’re doing work that matters. Help us solve what others can’t.
: Design of High Speed SERDES for UCIe products at data rates up to 64 Gbps on leading edge technology nodes (e.g. 2nm FinFET
experience and design experience at 10Gbps and in 16nm technologies * Collaborating with the Cadence R&D teams (Virtuoso, PVS
to make an impact on the world of technology. Job Title: Lead Analog Layout Design Engineer (SERDES/UCie) Location: Cork... Reports to: Sr Principal Engineer Job Overview: The Lead Analog L…
SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock
that matters. Help us solve what others can’t.
: Design of High Speed SERDES products at data rates up to and exceeding 112 Gbps on leading edge technology nodes (e.g. 5nm... in publishing academic papers and presenting at conferences e…
to make an impact on the world of technology. Job Title: Principal Analog Design Engineer (SERDES) Location: Cork... Reports to: Design Engineering Group Director Job Overview: The Principa…
SERDES circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock
that matters. Help us solve what others can’t.
Review Meetings and Checklist Reviews as part of ISO-9001. Represent Cadence in Standards Body Working Groups e.g. IEEE, PCI
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